The present invention relates generally to integrated circuits and, more particularly, to an integrated circuit for enabling lower voltage-rated devices to handle higher input voltages.
Analog functional modules (for example, an analog-to-digital converter (ADC) of a system on chip (SOC) device sometimes need to handle input voltages that exceed the voltage rating of the devices constituting the analog functional module. One known way of handling high analog input voltage ranges employs a resistor divider network connected at the front end of the analog module. However, the resistor divider network constitutes a continuous load on the input. Disconnecting the resistor divider network when the module is idle reduces the load but still leaves the component devices at risk of damage if a high voltage should appear on the input. A further disadvantage associated with use of a resistor divider network, particularly in the case of an ADC, is that the input voltage swing is reduced (typically by 50%) along with a potential signal to noise reduction of 6 db. Also, disadvantageously, a trade-off between speed and input loading (and gain error) has to be made by the designer.
Thus, it would be advantageous to provide a circuit for an analog device that enabled the analog device to handle higher voltages than the voltage ratings of its constituent devices without the need for a resistor divider network.